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HP C

HP C
User's Guide for OpenVMS Systems

Contents

Index

6.2.2.7 Generate Break Instruction ( __break)

The __break function generates a break instruction with an immediate.

This function has the following format:

void __break (const int __break_arg);

__break_arg
An immediate value for the __break instruction to use.

6.2.2.8 Serialize Data ( __dsrlz)

The __dsrlz function serializes data. Maps to the srlz.d instruction.

This function has the following format:

void __dsrlz (void);

6.2.2.9 Flush Cache Instruction ( __fc)

The __fc function flushes a cache line associated with the address given by the argument. Maps to the fcr instruction.

This function has the following format:

void __fc (__int64 __address);

__address
A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.10 Flush Write Buffers ( __fwb)

The __fwb function flushes the write buffers. Maps to the fwb instruction.

This function has the following format:

void __fwb (void);

6.2.2.11 Invalidate ALAT ( __invalat)

The __invalat function invalidates ALAT. Maps to the invala instruction.

This function has the following format:

void __invalat (void);

6.2.2.12 Invalidate ALAT ( __invala)

The __invala function is the same as the __invalat function.

6.2.2.13 Execute Serialize ( __isrlz)

The __isrlz function executes the serialize instruction. Maps to the srlz.i instruction.

This function has the following format:

void __isrlz (void);

6.2.2.14 Insert Data Address Translation Cache ( __itcd)

The __itcd function inserts an entry into the data translation cache. Maps to the itc.d instruction.

This function has the following format:

void __itcd (__int64 pa);

pa
A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.15 Insert Instruction Address Translation Cache ( __itci)

The __itci function inserts an entry into the instruction translation cache. Maps to the itc.i instruction.

This function has the following format:

void __itci (__int64 pa);

pa
A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.16 Insert Data Translation Register ( __itrd)

The __itrd function maps to the itr.d instruction.

This function has the following format:

void __itrd (__int64 whichTransReg, __int64 pa);

whichTransReg
The data translation register to be used by the itr.d instruction.
pa
A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.17 Insert Instruction Translation Register ( __itri)

The __itri function maps to the itr.i instruction.

This function has the following format:

void __itri (__int64 whichTransReg, __int64 pa);

whichTransReg
The data translation register to be used by the itr.i instruction.
pa
A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.18 Purge Translation Cache Entry ( __ptce)

The __ptce function maps to the ptc.e instruction.

This function has the following format:

void __ptce (__int64 va);

va
A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.19 Purge Global Translation Cache ( __ptcg)

The __ptcg function purges the global translation cache. Maps to the ptc.g r,r instruction.

This function has the following format:

void __ptcg (__int64 va, __int64 pagesz);

va
A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.
pagesz
The address range of the purge.

6.2.2.20 Purge Local Translation Cache ( __ptcl)

The __ptcl function purges the local translation cache. Maps to the ptc.l r,r instruction.

This function has the following format:

void __ptcl (__int64 va, __int64 pagesz);

va
A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.
pagesz
The address range of the purge.

6.2.2.21 Purge Global Translation Cache and ALAT ( __ptcga)

The __ptcga function purges the global translation cache and ALAT. Maps to the ptc.ga r,r instruction.

This function has the following format:

void __ptcga (__int64 va, __int64 pagesz);

va
A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.
pagesz
The address range of the purge.

6.2.2.22 Purge Data Translation Register ( __ptrd)

The __ptrd function purges the data translation register. Maps to the ptr.d r,r instruction.

This function has the following format:

void __ptrd (__int64 va, __int64 pagesz);

va
A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.
pagesz
The address range of the purge.

6.2.2.23 Purge Instruction Translation Register ( __ptri)

The __ptri function purges the instruction translation register. Maps to the ptr.i r,r instruction.

This function has the following format:

void __ptri (__int64 va, __int64 pagesz);

va
A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.
pagesz
The address range of the purge.

6.2.2.24 Reset System Mask ( __rsm)

The __rsm function resets the system mask bits of the PSR. Maps to the rsm imm24 instruction.

This function has the following format:

void __rsm (int mask);

mask
An integer value inserted into the instruction as a 24-bit immediate value.

6.2.2.25 Reset User Mask ( __rum)

The __rum function resets the user mask.

This function has the following format:

void __rum (int mask);

mask
An integer value inserted into the instruction as a 24-bit immediate value.

6.2.2.26 Set System Mask ( __ssm)

The __ssm function sets the system mask.

This function has the following format:

void __ssm (int mask);

mask
An integer value inserted into the instruction as a 24-bit immediate value.

6.2.2.27 Set User Mask ( __sum)

The __sum function sets the user mask bits of the PSR. Maps to the sum imm24 instruction.

This function has the following format:

void __sum (int mask);

mask
An integer value inserted into the instruction as a 24-bit immediate value.

6.2.2.28 Enable Memory Synchronization ( __synci)

The __synci function enables memory synchronization. Maps to the sync.i instruction.

This function has the following format:

void __synci (void);

6.2.2.29 Translation Hashed Entry Address ( __thash)

The __thash function generates a translation hash entry address. Maps to the thash r = r instruction.

This function has the following format:

void __thash(__int64 __address);

__address
A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.30 Translation Hashed Entry Tag ( __ttag)

The __ttag function generates a translation hash entry tag. Maps to the ttag r=r instruction.

This function has the following format:

void __ttag(__int64 __address);

__address
A 64-bit address, as opposed to a 32-bit or 64-bit pointer, that is loaded into a 64-bit general register used by the instruction to be generated.

6.2.2.31 Atomic Compare and Exchange ( _InterlockedCompareExchange_acq)

The _InterlockedCompareExchange_acq function atomically compares and exchanges the value specified by the first argument (a 64-bit pointer). This function maps to the cmpxchg4.acq instruction with appropriate setup.

This function has the following format:

unsigned __int64 _InterlockedCompareExchange_acq (volatile unsigned int *Destination,
unsigned __int64 Newval, unsigned __int64 Comparand);

The value at *Destination is compared with the value specified by Comparand. If they are equal, Newval is written to *Destination, and Oldval is returned. The exchange will have taken place if the value returned is equal to the Comparand. The following algorithm is used:

ar.ccv = Comparand; Oldval = *Destination; //Atomic if (ar.ccv == *Destination) //Atomic *Destination = Newval; //Atomic return Oldval;

Those parts of the algorithm that are marked "Atomic" are performed atomically by the cmpxchg4.acq instruction. This instruction has acquire ordering semantics; that is, the memory read/write is made visible prior to all subsequent data memory accesses of the Destination by other processors.

Destination
The value to be compared with Comparand and, if equal, replaced with the value of Newval.
Newval
The new value to replace the value in Destination.
Comparand
The value with which to compare Destination.

6.2.2.32 Atomic Compare and Exchange ( _InterlockedCompareExchange64_acq)

The _InterlockedCompareExchange64_acq function is the same as the _InterlockedCompareExchange_acq function, except that those parts of the algorithm that are marked "Atomic" are performed by the cmpxchg8.acq instruction.

This function has the following format:

unsigned __int64 _InterlockedCompareExchange64_acq (volatile unsigned __int64 *Destination,
unsigned __int64 Newval, unsigned __int64 Comparand);

6.2.2.33 Atomic Compare and Exchange ( _InterlockedCompareExchange_rel)

This function is the same as the _InterlockedCompareExchange_acq function except that those parts of the algorithm that are marked "Atomic" are performed by the cmpxchg4.rel instruction with release ordering semantics; that is, the memory read/write is made visible after all previous memory accesses of the Destination by other processors.

This function has the following format:

unsigned __int64 _InterlockedCompareExchange_rel (volatile unsigned int *Destination,
unsigned __int64 Newval, unsigned __int64 Comparand);

6.2.2.34 Atomic Compare and Exchange ( _InterlockedCompareExchange64_rel)

This function is the same as the _InterlockedCompareExchange_rel function, except that those parts of the algorithm that are marked "Atomic" are performed by the cmpxchg8.rel instruction.

This function has the following format:

unsigned __int64 _InterlockedCompareExchange64_rel (volatile unsigned __int64 *Destination,
unsigned __int64 Newval, unsigned __int64 Comparand);

6.2.2.35 Conditional Atomic Compare and Exchange Longword (__CMP_SWAP_LONG)

The __CMP_SWAP_LONG function performs a conditional atomic compare and exchange operation on a longword. The longword pointed to by source is read and compared with the longword old_value. If they are equal, the longword new_value is written into the longword pointed to by source. The read and write is performed atomically, with no intervening access to the same memory region.