Arguments

 

invo_handle

   OpenVMS usage:invo_handle
   type:         quadword (unsigned)
   access:       read only
   mechanism:    by reference

   Handle for the invocation to be updated.
 

invo_context

   OpenVMS usage:invo_context_blk
   type:         structure
   access:       read only
   mechanism:    by reference

   Address of a valid invocation context block that contains new
   register contents.

   Each register that is set in the xx_mask argument (along with
   its NaT bit, if any) is updated using the value found in the
   corresponding IREG[n], FREG[n], BRANCH[n], or PRED[n] field. GP,
   TP, and AI can also be updated in this way.

   No other fields of the invocation context block are used.
 

gr_mask

   OpenVMS usage:mask_octaword
   type:         128-bit vector
   access:       read only
   mechanism:    by reference

   Address of a 128-bit bit vector, where each bit corresponds to a
   register field in the invo_context argument. Bits 0 through 127
   correspond to IREG[0] through IREG[127].

   Bit 0 corresponds to R0, which cannot be written, and is ignored.

   Bit 1 corresponds to the global data pointer (GP).

   Bit 13 corresponds to the thread pointer (TP).

   Bit 25 corresponds to the argument information register (AI).

   If bit 12, which corresponds to SP, is set, then no changes are
   made.
 

fr_mask

   OpenVMS usage:mask_octaword
   type:         128-bit vector
   access:       read only
   mechanism:    by reference

   Address of a 128-bit bit vector, where each bit corresponds to a
   register field in the passed invo_context.

   To update floating-point registers F32-F127, provide a pointer to
   an array of 96 octawords in LIBICB$PH_F32_F127.

   Bits 0 through 127 correspond to FREG[0] through FREG[127].

   Bit 0 corresponds to F0, which cannot be written, and is ignored.
   Bit 1 corresponds to F1, which cannot be written, and is ignored.
 

br_mask

   OpenVMS usage:mask_byte
   type:         8-bit vector
   access:       read only
   mechanism:    by reference

   Address of a 8-bit bit vector, where each bit corresponds to
   a register field in the passed invo_context. Bits 0 through 7
   correspond to BRANCH[0] through BRANCH[7].
 

pr_mask

   OpenVMS usage:mask_quadword
   type:         64-bit vector
   access:       read only
   mechanism:    by reference

   Address of a 64-bit bit vector, where each bit corresponds to
   a register field in the passed invo_context. Bits 0 through 63
   correspond to PRED[0] through PRED[63].
 

misc_mask

   OpenVMS usage:mask_quadword
   type:         64-bit vector
   access:       read only
   mechanism:    by reference

   Address of a 64-bit bit vector, where each bit corresponds to a
   register field in the passed invo_context as follows:

      Bit 0=PC.
      Bit 1=FPSR.
      Bits 2-63 are reserved.