/* // Note: This header is use by both the CC compiler and the IA64 // assembler (via the CC preprocessor which creates the // IA64 assembler source file). // // The CC portion of this header starts at the comment line // 'CC header begins here'. // // ----------------------------------------------------------------------------- */ #ifdef IAS_ASSEMBLER /* IA64 assembler header begins here */ /* ************************************************************************* */ /* * * */ /* * HP CONFIDENTIAL. This software is confidential proprietary software * */ /* * licensed by Hewlett-Packard Development Company, L.P., and is not * */ /* * authorized to be used, duplicated OR disclosed to anyone without the * */ /* * prior written permission of HP. * */ /* * © 2021 Copyright Hewlett-Packard Development Company, L.P. * */ /* * * */ /* * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential * */ /* * proprietary software licensed by VMS Software, Inc., and is not * */ /* * authorized to be used, duplicated or disclosed to anyone without * */ /* * the prior written permission of VMS Software, Inc. * */ /* * © 2021 Copyright VMS Software, Inc. * */ /* * * */ /* ************************************************************************* */ /* ******************************************************************************************************************************** */ /* Created: 9-Mar-2021 22:28:10 by OpenVMS SDL EV3-3 */ /* Source: 08-JUN-2004 15:02:05 $1$DGA8085:[STARLET_H.SRC]PRDEF.SDL;1 */ /* ******************************************************************************************************************************** */ /* .MACRO $PRDEF,$GBL */ /* $DEFINI PR,$GBL */ /* + */ /* PROCESSOR REGISTER DEFINITIONS */ /* */ /* The following IPR symbols are provided for the convenience */ /* of common Macro-32 code using the VAX MFPR/MTPR instructions */ /* to operate against IPRs that exist in both architectures */ /* architectures. Even Alpha-specific Macro-32 code would benefit */ /* since the compiler can calculate register live-ness around the */ /* VAX MFPR/MTPR instructions. */ /* */ /* The assigned values for the PR$_ipr symbols match the VAX */ /* IPR numbers themselves wherever possible. VAX IPR numbers that */ /* are extremely unlikely ever to be encountered are otherwise used. */ /* The compiler uses the VAX values to validate the invocation of */ /* MTPR/MFPR instructions. */ /* - */ #define PR$_ESP 1 /* Executive Stack Pointer */ #define PR$_SSP 2 /* Supervisor Stack Pointer */ #define PR$_USP 3 /* User Stack Pointer */ #define PR$_ASN 6 /* Address Space Number */ #define PR$_ASTEN 48 /* AST Enabled Register (MFPR only) */ #define PR$_ASTSR 49 /* AST Summary Register (MFPR only) */ #define PR$_DATFX 23 /* Data Alignment Trap Fixup in PALcode Enable */ #define PR$_IPIR 22 /* Interprocess Interrupt Request */ #define PR$_IPL 18 /* Interrupt Priority Level */ #define PR$_MCES 38 /* Machine Check Error Summary */ #define PR$_PCBB 16 /* Privileged Context Block Base */ #define PR$_PME 61 /* Performance Monitor Enable */ #define PR$_PRBR 15 /* Processor Base Register */ #define PR$_SCBB 17 /* System Control Block Base */ #define PR$_SIRR 20 /* Software Interrupt Request */ #define PR$_SISR 21 /* Software Interrupt Summary */ #define PR$_TBIA 57 /* Translation Buffer Invalidate All */ #define PR$_TBIAP 50 /* Translation Buffer Invalidate All Process */ #define PR$_TBIS 58 /* Translation Buffer Invalidate Single - 32 bit VA */ #define PR$_TBIS_64 60 /* Translation Buffer Invalidate Single - 64 bit VA */ #define PR$_TBISD 59 /* Translation Buffer Invalidate Single - 64 bit VA - D-stream only */ #define PR$_TBISI 47 /* Translation Buffer Invalidate Single - 64 bit VA - I-stream only */ #define PR$_VPTB 12 /* Virtual Page Table Base Register */ /* + */ /* PROCESSOR REGISTER FIELD DEFINITIONS */ /* - */ #define PR$_SID_TYP780 1 /* VAX 11/780 */ #define PR$_SID_TYP750 2 /* VAX 11/750 */ #define PR$_SID_TYP730 3 /* VAX 11/730 */ #define PR$_SID_TYP790 4 /* VAX 11/790 */ #define PR$_SID_TYP8SS 5 /* Scorpio for now */ #define PR$_SID_TYP8NN 6 /* Nautilus for now */ #define PR$_SID_TYPUV1 7 /* MicroVAX I */ #define PR$_SID_TYPUV2 8 /* MicroVAX II */ #define PR$_SID_TYP410 8 /* VAXstar */ #define PR$_SID_TYP009 9 /* Virtual VAX */ #define PR$_SID_TYP420 10 /* PVAX */ #define PR$_SID_TYP520 10 /* Cirrus I */ #define PR$_SID_TYP650 10 /* Mayfair */ #define PR$_SID_TYP9CC 10 /* Calypso/XCP */ #define PR$_SID_TYP9CI 10 #define PR$_SID_TYP60 10 /* Firefox */ #define PR$_SID_TYP670 11 /* KA670 (Pele) */ #define PR$_SID_TYP9RR 11 /* XRP */ #define PR$_SID_TYP43 11 /* KA43 (RigelMAX) */ #define PR$_SID_TYP9AQ 14 /* Aquarius */ #define PR$_SID_TYP8PS 17 /* Polarstar */ #define PR$_SID_TYP1202 18 /* Mariah/XMP */ #define PR$_SID_TYP46 18 /* PV-Mariah */ #define PR$_SID_TYP600 19 #define PR$_SID_TYP690 19 #define PR$_SID_TYP700 19 #define PR$_SID_TYP1302 19 #define PR$_SID_TYP49 19 #define PR$_SID_TYP1303 19 #define PR$_SID_TYP660 20 /* KA660 (Spitfire) */ #define PR$_SID_TYP440 20 /* PVAX2 */ #define PR$_SID_TYP4A 20 /* PCVAX */ #define PR$_SID_TYP550 20 /* Cirrus II */ #define PR$_SID_TYP1701 23 /* Laser/Neon */ #define PR$_SID_TYPMAX 23 /* MAX LEGAL CPU TYPE */ #define PR$_SID_TYP_NOTAVAX 128 /* Not a VAX (i.e. Alpha or some such) */ /* Chip CPU types */ #define PR$_SID_TYPUV 8 /* MicroVAX chip */ /* MicroVAX chip CPU Subtypes */ #define PR$_XSID_UV_UV 0 /* Generic MicroVAX (unused subtype) */ #define PR$_XSID_UV_UV2 1 /* MicroVAX II */ #define PR$_XSID_UV_410 4 /* VAXstar */ #define PR$_SID_TYPCV 10 /* CVAX chip */ /* CVAX chip CPU Subtypes */ #define PR$_XSID_CV_CV 0 /* Generic CVAX (unused subtype) */ #define PR$_XSID_CV_650 1 /* Mayfair */ #define PR$_XSID_CV_9CC 2 /* Calypso/XCP */ #define PR$_XSID_CV_60 3 /* Firefox */ #define PR$_XSID_CV_420 4 /* PVAX */ #define PR$_XSID_CV_9CI 5 #define PR$_XSID_CV_520 7 /* CIRRUS I */ #define PR$_SID_TYPRV 11 /* Rigel chip */ /* Rigel chip CPU Subtypes */ #define PR$_XSID_RV_RV 0 /* Generic Rigel (unused subtype) */ #define PR$_XSID_RV_670 1 /* KA670 (Pele) */ #define PR$_XSID_RV_9RR 2 /* Calypso/XRP */ #define PR$_XSID_RV_43 4 /* KA43 (RigelMAX) */ #define PR$_SID_TYPV12 18 /* Mariah chip set */ /* Mariah chip CPU Subtypes */ #define PR$_XSID_V12_V12 0 /* Generic Mariah (unused subtype) */ #define PR$_XSID_V12_1202 2 /* MARIAH/XMP */ #define PR$_XSID_V12_46 4 /* PVAX- mariah subtype */ #define PR$_SID_TYPV13 19 #define PR$_XSID_V13_V13 0 #define PR$_XSID_V13_690 1 #define PR$_XSID_V13_1302 2 #define PR$_XSID_V13_1303 3 #define PR$_XSID_V13_49 4 #define PR$_XSID_V13_700 5 #define PR$_XSID_V13_600 6 #define PR$_SID_TYPV14 20 /* SOC Chip SID */ /* SOC chip CPU subtypes */ #define PR$_XSID_V14_V14 0 /* unused subtype */ #define PR$_XSID_V14_660 1 /* KA660 (Spitfire) */ #define PR$_XSID_V14_440 4 /* PVAX2 subtype */ #define PR$_XSID_V14_4A 5 /* PCVAX subtype */ #define PR$_XSID_V14_550 7 /* CIRRUS II */ #define PR$_SID_TYPV17 23 /* NVAX+ Chip SID */ /* NVAX+ chip CPU subtypes */ #define PR$_XSID_V17_V17 0 /* unused subtype */ #define PR$_XSID_V17_1701 1 /* Laser/Neon */ /* Nautilus CPU Subtypes */ #define PR$_XSID_N8800 0 /* VAX 8800 */ #define PR$_XSID_N8700 1 /* VAX 8700 */ #define PR$_XSID_N2 2 /* Undefined Nautilus CPU */ #define PR$_XSID_N3 3 /* Undefined Nautilus CPU */ #define PR$_XSID_N4 4 /* Undefined Nautilus CPU */ #define PR$_XSID_N5 5 /* Undefined Nautilus CPU */ #define PR$_XSID_N8550 6 /* VAX 8550 */ #define PR$_XSID_N8500 7 /* VAX 8500 */ #define PR$_XSID_N8NNN -1 /* Unknown Nautilus CPU */ /* ------------------------------------------------------------------- */ #define PR$M_ASTEN 0xF #define PR$M_ASTEN_KEN 0x1 #define PR$M_ASTEN_EEN 0x2 #define PR$M_ASTEN_SEN 0x4 #define PR$M_ASTEN_UEN 0x8 #define PR$M_ASTEN_DSBL_ALL 0 /* Disable all ASTs */ #define PR$M_ASTEN_ENBL_ALL 255 /* Enable all ASTs */ #define PR$M_ASTEN_ENBL_K 17 /* Enable kernel ASTs */ #define PR$M_ASTEN_ENBL_E 34 /* Enable executive ASTs */ #define PR$M_ASTEN_ENBL_S 68 /* Enable supervisor ASTs */ #define PR$M_ASTEN_ENBL_U 136 /* Enable user ASTs */ #define PR$M_ASTEN_PRSRV_ALL 15 /* Preserve all enable/disable states */ #define PR$M_ASTEN_PRSRV_K 1 /* Preserve kernel enable/disable */ #define PR$M_ASTEN_PRSRV_E 2 /* Preserve executive enable/disable */ #define PR$M_ASTEN_PRSRV_S 4 /* Preserve supervisor enable/disable */ #define PR$M_ASTEN_PRSRV_U 8 /* Preserve user enable/disable */ /* ------------------------------------------------------------------- */ #define PR$M_ASTSR 0xF #define PR$M_ASTSR_KPD 0x1 #define PR$M_ASTSR_EPD 0x2 #define PR$M_ASTSR_SPD 0x4 #define PR$M_ASTSR_UPD 0x8 #define PR$M_ASTSR_CLR_ALL 0 /* Clear pending ASTs */ #define PR$M_ASTSR_SET_ALL 255 /* Set all ASTs pending */ #define PR$M_ASTSR_SET_K 17 /* Set kernel AST pending */ #define PR$M_ASTSR_SET_E 34 /* Set executive AST pending */ #define PR$M_ASTSR_SET_S 68 /* Set supervisor AST pending */ #define PR$M_ASTSR_SET_U 136 /* Set user AST pending */ #define PR$M_ASTSR_PRSRV_ALL 15 /* Preserve all pending bits */ #define PR$M_ASTSR_PRSRV_K 1 /* Preserve kernel pending */ #define PR$M_ASTSR_PRSRV_E 2 /* Preserve executive pending */ #define PR$M_ASTSR_PRSRV_S 4 /* Preserve supervisor pending */ #define PR$M_ASTSR_PRSRV_U 8 /* Preserve user pending */ /* ------------------------------------------------------------------- */ #define PR$M_FEN_FEN 0x1 #define PR$M_DATFX_DATFX 0x1 #define PR$M_IPL_IPL 0x1F #define PR$M_MCES_MCK 0x1 #define PR$M_MCES_SCE 0x2 #define PR$M_MCES_PCE 0x4 #define PR$M_MCES_DPC 0x8 #define PR$M_MCES_DSC 0x10 #define PR$V_PCBB_PA 0 /* HWPCB Physical Address */ #define PR$S_PCBB_PA 48 /* HWPCB Physical Address */ /* ------------------------------------------------------------------- */ #define PR$M_PS_SW 0x3 #define PR$M_PS_PRVMOD 0x3 #define PR$M_PS_SYSSTATE 0x4 #define PR$M_PS_CURMOD 0x18 #define PR$M_PS_VMM 0x80 #define PR$M_PS_IPL 0x1F00 #define PR$M_PS_SP_ALIGN 0x3F00000000000000 #define PR$M_PS_MBZ_62 0x4000000000000000 #define PR$M_PS_MBZ_63 0x8000000000000000 #define PR$V_PS_MAX_PS_REG_BIT 13 /* */ #define PR$C_PS_KERNEL 0 /* Kernel Mode */ #define PR$C_PS_EXEC 1 /* Executive Mode */ #define PR$C_PS_SUPER 2 /* Supervisor Mode */ #define PR$C_PS_USER 3 /* User Mode */ /* ------------------------------------------------------------------- */ #define PR$M_PTBR_PFN 0xFFFFFFFF #define PR$M_SCBB_PFN 0xFFFFFFFF #define PR$M_SIRR_LVL 0xF #define PR$M_SISR_SUMMARY 0xFFFF #define PR$M_SISR_RAZ 0x1 #define PR$M_SISR_IR1 0x2 #define PR$M_SISR_IR2 0x4 #define PR$M_SISR_IR3 0x8 #define PR$M_SISR_IR4 0x10 #define PR$M_SISR_IR5 0x20 #define PR$M_SISR_IR6 0x40 #define PR$M_SISR_IR7 0x80 #define PR$M_SISR_IR8 0x100 #define PR$M_SISR_IR9 0x200 #define PR$M_SISR_IR10 0x400 #define PR$M_SISR_IR11 0x800 #define PR$M_SISR_IR12 0x1000 #define PR$M_SISR_IR13 0x2000 #define PR$M_SISR_IR14 0x4000 #define PR$M_SISR_IR15 0x8000 #define PR$M_TBCHK_VA_PRESENT 0x1 #define PR$M_IEEE_DNOD 0x800000000000 #define PR$M_IEEE_DNZ 0x1000000000000 #define PR$M_IEEE_INVD 0x2000000000000 #define PR$M_IEEE_DZED 0x4000000000000 #define PR$M_IEEE_OVFD 0x8000000000000 #define PR$M_IEEE_INV 0x10000000000000 #define PR$M_IEEE_DZE 0x20000000000000 #define PR$M_IEEE_OVF 0x40000000000000 #define PR$M_IEEE_UNF 0x80000000000000 #define PR$M_IEEE_INE 0x100000000000000 #define PR$M_IEEE_IOV 0x200000000000000 #define PR$M_IEEE_UNDZ 0x1000000000000000 #define PR$M_IEEE_UNFD 0x2000000000000000 #define PR$M_IEEE_INED 0x4000000000000000 #define PR$M_IEEE_SUMMARY 0x8000000000000000 #define PR$S_PRDEF 8 #define PR$S_QUAD_ACCESS 8 #define PR$Q_QUAD_ACCESS 0 /* Access to register as a quadword */ #define PR$S_LONG_ACCESS 8 #define PR$L_LONG_ACCESS 0 /* Access to register as a quadword */ #define PR$S_SID_SN 12 #define PR$V_SID_SN 0 /* SERIAL NUMBER FIELD */ #define PR$S_SID_PL 3 #define PR$V_SID_PL 12 /* PLANT ID */ #define PR$S_SID_ECO 9 #define PR$V_SID_ECO 15 /* ECO LEVEL */ #define PR$S_SID_TYPE 8 #define PR$V_SID_TYPE 24 /* CPU TYPE CODE */ #define PR$S_XSID_TYPE 8 #define PR$V_XSID_TYPE 24 /* CPU SUBTYPE CODE */ /* SYSTEM ID REGISTER CPU TYPES */ /* Number assignments are */ /* based upon the jumpers */ /* read by the console from */ /* the MPS backplane */ /* ASTEN - AST Enabled Register */ /* */ /* NOTE WELL: These bit symbols are to be used only when interfacing to the */ /* ASTEN internal processor register. They are NOT to be used when */ /* interfacing to the copy of ASTEN which is stored in the Hardware */ /* Privileged Context Block (HWPCB). See the HWPCB-specific symbols */ /* for how to refer to the ASTEN field in the HWPCB. */ /* */ #define PR$S_ASTEN 4 #define PR$V_ASTEN 0 /* Enabled AST mask */ #define PR$V_ASTEN_KEN 0 /* Kernel AST Enabled */ #define PR$V_ASTEN_EEN 1 /* Executive AST Enabled */ #define PR$V_ASTEN_SEN 2 /* Supervisor AST Enabled */ #define PR$V_ASTEN_UEN 3 /* User AST Enabled */ /* ASTSR - AST Summary Register */ /* */ /* NOTE WELL: These bit symbols are to be used only when interfacing to the */ /* ASTSR internal processor register. They are NOT to be used when */ /* interfacing to the copy of ASTSR which is stored in the Hardware */ /* Privileged Context Block (HWPCB). See the HWPCB-specific symbols */ /* for how to refer to the ASTSR field in the HWPCB. */ /* */ #define PR$S_ASTSR 4 #define PR$V_ASTSR 0 /* AST pending summary mask */ #define PR$V_ASTSR_KPD 0 /* Kernel AST Pending */ #define PR$V_ASTSR_EPD 1 /* Executive AST Pending */ #define PR$V_ASTSR_SPD 2 /* Supervisor AST Pending */ #define PR$V_ASTSR_UPD 3 /* User AST Pending */ /* FEN - Floating Point Enable */ /* */ /* NOTE WELL: These bit symbols are to be used only when interfacing to the */ /* FEN internal processor register. They are NOT to be used when */ /* interfacing to the copy of FEN which is stored in the Hardware */ /* Privileged Context Block (HWPCB). See the HWPCB-specific symbols */ /* for how to refer to the FEN field in the HWPCB. */ /* */ #define PR$V_FEN_FEN 0 /* Floating point enabled = 1 */ /* ------------------------------------------------------------------- */ /* DATFX - Data Alignment Trap Fixup */ /* */ #define PR$V_DATFX_DATFX 0 /* Data Alignment Trap Fixup */ /* ------------------------------------------------------------------- */ /* IPL - Interrupt Priority Level */ /* */ #define PR$S_IPL_IPL 5 #define PR$V_IPL_IPL 0 /* Interrupt Priority Level */ /* ------------------------------------------------------------------- */ /* MCES - Machine Check Error Summary Register */ /* */ #define PR$V_MCES_MCK 0 /* Machine Check (W1C) */ #define PR$V_MCES_SCE 1 /* System Correctable Error (W1C) */ #define PR$V_MCES_PCE 2 /* Processor Correctable Error (W1C) */ #define PR$V_MCES_DPC 3 /* Disable Processor Correctable Error report */ #define PR$V_MCES_DSC 4 /* Disable System Correctable Error report */ /* ------------------------------------------------------------------- */ /* PCBB - Privileged Context Block Base */ /* */ /* PS - Processor Status */ /* */ /* The PS is not an IPR in the sense that it isn't read/written using */ /* the MxPR operators. However, the bitfields of the PS are defined */ /* here since this is the repository for bitfields of architected IPRs, */ /* hence it's convenient to define them here. */ /* */ /* Although the 'software' field of the PS is not privileged state and */ /* may be used by users as they see fit in User mode, VMS imposes a */ /* privileged interpretation on the bits when used in any of the three */ /* inner processor modes (Kernel, Executive, Supervisor). There are */ /* consequences of this: */ /* */ /* 1) Should User mode code be using the software field bits, it */ /* must be assumed that the User mode setting of these */ /* bits are entirely ignored by inner mode software. */ /* */ /* 2) VMS reserves the right to redefine its privileged (inner */ /* mode) interpretation of these bits at any time. */ /* */ #define PR$S_PS_SW 2 #define PR$V_PS_SW 0 /* Software Bits */ #define PR$S_PS_PRVMOD 2 #define PR$V_PS_PRVMOD 0 /* Previous Processor Mode */ #define PR$V_PS_SYSSTATE 2 /* System State Indicator */ #define PR$S_PS_CURMOD 2 #define PR$V_PS_CURMOD 3 /* Current Processor Mode */ #define PR$V_PS_VMM 7 /* Virtual Machine Monitor */ #define PR$S_PS_IPL 5 #define PR$V_PS_IPL 8 /* Interrupt Priority Level */ #define PR$S_PS_SP_ALIGN 6 #define PR$V_PS_SP_ALIGN 56 /* Stack Pointer Alignment */ #define PR$V_PS_MBZ_62 62 /* Reserved bit above SP alignment */ #define PR$V_PS_MBZ_63 63 /* Reserved bit above SP alignment */ /* */ /* Maximum bit number used in the PS register */ /* */ /* MODE SYMBOL DEFINITIONS */ /* */ /* PTBR - Page Table Base Register */ /* */ #define PR$S_PTBR_PFN 32 #define PR$V_PTBR_PFN 0 /* PFN of current L1PT */ /* ------------------------------------------------------------------- */ /* SCBB - System Control Block Base */ /* */ #define PR$S_SCBB_PFN 32 #define PR$V_SCBB_PFN 0 /* PFN of SCB */ /* ------------------------------------------------------------------- */ /* SIRR - Software Interrupt Request Register */ /* */ #define PR$S_SIRR_LVL 4 #define PR$V_SIRR_LVL 0 /* Software Interrupt Request Level */ /* ------------------------------------------------------------------- */ /* SISR - Software Interrupt Summary Register */ /* */ #define PR$S_SISR_SUMMARY 16 #define PR$V_SISR_SUMMARY 0 /* Sofware Interrupt Summary */ #define PR$V_SISR_IR1 1 /* Softint 1 pending */ #define PR$V_SISR_IR2 2 /* Softint 2 pending */ #define PR$V_SISR_IR3 3 /* Softint 3 pending */ #define PR$V_SISR_IR4 4 /* Softint 4 pending */ #define PR$V_SISR_IR5 5 /* Softint 5 pending */ #define PR$V_SISR_IR6 6 /* Softint 6 pending */ #define PR$V_SISR_IR7 7 /* Softint 7 pending */ #define PR$V_SISR_IR8 8 /* Softint 8 pending */ #define PR$V_SISR_IR9 9 /* Softint 9 pending */ #define PR$V_SISR_IR10 10 /* Softint 10 pending */ #define PR$V_SISR_IR11 11 /* Softint 11 pending */ #define PR$V_SISR_IR12 12 /* Softint 12 pending */ #define PR$V_SISR_IR13 13 /* Softint 13 pending */ #define PR$V_SISR_IR14 14 /* Softint 14 pending */ #define PR$V_SISR_IR15 15 /* Softint 15 pending */ /* ------------------------------------------------------------------- */ /* TBCHK - Translation Buffer Check */ /* */ /* This IPR may always be referenced with MFPR without causing an error */ /* to occur (unlike VAX), but the feature provided by TBCHK may or may */ /* not be implemented. If not, then =1 and */ /* should be ignored. If TBCHK's function IS implemented, then */ /* =0 and returns the desired data. */ /* */ __struct { unsigned pr$v_tbchk_va_present : 1; /* VA in TB = 1 */ unsigned pr$v_fill_1 : 31; unsigned pr$v_fill_2 : 31; unsigned pr$v_tbchk_no_tbchk : 1; /* Not implemented = 1 */ } pr$r_tbchk_bits; /*------------------------------------------------------------------- */ /* FPCR - Floating Point Control Register */ /* */ /* NOTE WELL: These bit symbols are to be used only when interfacing to the */ /* hardware FPCR internal processor register. They are NOT to be used when */ /* interfacing to the software floating point control register pointed to */ /* by CTL$GQ_IEEE_FP_CONTROL/PKTA$Q_IEEE_FP_CONTROL. */ /* */ /* The hardware FPCR should only be manipulated via the system service, */ /* SYS$IEEE_FP_CONTROL, rather than directly. */ /* */ __struct { unsigned pr$v_fpcr_fill_1 : 32; unsigned pr$v_fpcr_fill_2 : 15; unsigned pr$v_ieee_dnod : 1; /* Denormal operand exception disable */ unsigned pr$v_ieee_dnz : 1; /* Denormal operands to 0.0 */ unsigned pr$v_ieee_invd : 1; /* Invalid operation disable */ unsigned pr$v_ieee_dzed : 1; /* Division by zero disable */ unsigned pr$v_ieee_ovfd : 1; /* Overflow disable */ unsigned pr$v_ieee_inv : 1; /* Invalid operation. */ unsigned pr$v_ieee_dze : 1; /* Division by zero occured. */ unsigned pr$v_ieee_ovf : 1; /* Overflow occured. */ unsigned pr$v_ieee_unf : 1; /* Underflow occured. */ unsigned pr$v_ieee_ine : 1; /* Inexact result occured. */ unsigned pr$v_ieee_iov : 1; /* Integer overflow occured */ unsigned pr$v_ieee_dyn_rnd : 2; /* Dynamic Rounding mode */ unsigned pr$v_ieee_undz : 1; /* Underflow to zero */ unsigned pr$v_ieee_unfd : 1; /* Underflow disable */ unsigned pr$v_ieee_ined : 1; /* Inexact disable */ unsigned pr$v_ieee_summary : 1; /* Bitwise OR of FPCR exception bits */ } pr$r_fpcr_bits; } PRDEF; #if !defined(__VAXC) #define pr$v_sid_sn pr$r_prdef_bits.pr$v_sid_sn #define pr$v_sid_pl pr$r_prdef_bits.pr$v_sid_pl #define pr$v_sid_eco pr$r_prdef_bits.pr$v_sid_eco #define pr$v_sid_type pr$r_prdef_bits.pr$v_sid_type #define pr$v_xsid_type pr$r_prdef_xbits.pr$v_xsid_type #define pr$v_asten pr$r_asten_def.pr$v_asten #define pr$v_asten_ken pr$r_asten_def.pr$r_asten_bits.pr$v_asten_ken #define pr$v_asten_een pr$r_asten_def.pr$r_asten_bits.pr$v_asten_een #define pr$v_asten_sen pr$r_asten_def.pr$r_asten_bits.pr$v_asten_sen #define pr$v_asten_uen pr$r_asten_def.pr$r_asten_bits.pr$v_asten_uen #define pr$v_astsr pr$r_astsr_def.pr$v_astsr #define pr$v_astsr_kpd pr$r_astsr_def.pr$r_astsr_bits.pr$v_astsr_kpd #define pr$v_astsr_epd pr$r_astsr_def.pr$r_astsr_bits.pr$v_astsr_epd #define pr$v_astsr_spd pr$r_astsr_def.pr$r_astsr_bits.pr$v_astsr_spd #define pr$v_astsr_upd pr$r_astsr_def.pr$r_astsr_bits.pr$v_astsr_upd #define pr$v_mces_mck pr$r_mces_overlay.pr$v_mces_mck #define pr$v_mces_sce pr$r_mces_overlay.pr$v_mces_sce #define pr$v_mces_pce pr$r_mces_overlay.pr$v_mces_pce #define pr$v_mces_dpc pr$r_mces_overlay.pr$v_mces_dpc #define pr$v_mces_dsc pr$r_mces_overlay.pr$v_mces_dsc #define pr$v_ps_sw pr$r_ps_swdef_bits.pr$v_ps_sw #define pr$v_ps_prvmod pr$r_psdef_bits.pr$v_ps_prvmod #define pr$v_ps_sysstate pr$r_psdef_bits.pr$v_ps_sysstate #define pr$v_ps_curmod pr$r_psdef_bits.pr$v_ps_curmod #define pr$v_ps_vmm pr$r_psdef_bits.pr$v_ps_vmm #define pr$v_ps_ipl pr$r_psdef_bits.pr$v_ps_ipl #define pr$v_ps_sp_align pr$r_psdef_bits.pr$v_ps_sp_align #define pr$v_ps_mbz_62 pr$r_psdef_bits.pr$v_ps_mbz_62 #define pr$v_ps_mbz_63 pr$r_psdef_bits.pr$v_ps_mbz_63 #define pr$v_sisr_summary pr$r_sisr_fields.pr$v_sisr_summary #define pr$v_sisr_ir1 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir1 #define pr$v_sisr_ir2 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir2 #define pr$v_sisr_ir3 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir3 #define pr$v_sisr_ir4 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir4 #define pr$v_sisr_ir5 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir5 #define pr$v_sisr_ir6 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir6 #define pr$v_sisr_ir7 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir7 #define pr$v_sisr_ir8 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir8 #define pr$v_sisr_ir9 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir9 #define pr$v_sisr_ir10 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir10 #define pr$v_sisr_ir11 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir11 #define pr$v_sisr_ir12 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir12 #define pr$v_sisr_ir13 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir13 #define pr$v_sisr_ir14 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir14 #define pr$v_sisr_ir15 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir15 #define pr$v_tbchk_va_present pr$r_tbchk_bits.pr$v_tbchk_va_present #define pr$v_tbchk_no_tbchk pr$r_tbchk_bits.pr$v_tbchk_no_tbchk #define pr$v_ieee_dnod pr$r_fpcr_bits.pr$v_ieee_dnod #define pr$v_ieee_dnz pr$r_fpcr_bits.pr$v_ieee_dnz #define pr$v_ieee_invd pr$r_fpcr_bits.pr$v_ieee_invd #define pr$v_ieee_dzed pr$r_fpcr_bits.pr$v_ieee_dzed #define pr$v_ieee_ovfd pr$r_fpcr_bits.pr$v_ieee_ovfd #define pr$v_ieee_inv pr$r_fpcr_bits.pr$v_ieee_inv #define pr$v_ieee_dze pr$r_fpcr_bits.pr$v_ieee_dze #define pr$v_ieee_ovf pr$r_fpcr_bits.pr$v_ieee_ovf #define pr$v_ieee_unf pr$r_fpcr_bits.pr$v_ieee_unf #define pr$v_ieee_ine pr$r_fpcr_bits.pr$v_ieee_ine #define pr$v_ieee_iov pr$r_fpcr_bits.pr$v_ieee_iov #define pr$v_ieee_dyn_rnd pr$r_fpcr_bits.pr$v_ieee_dyn_rnd #define pr$v_ieee_undz pr$r_fpcr_bits.pr$v_ieee_undz #define pr$v_ieee_unfd pr$r_fpcr_bits.pr$v_ieee_unfd #define pr$v_ieee_ined pr$r_fpcr_bits.pr$v_ieee_ined #define pr$v_ieee_summary pr$r_fpcr_bits.pr$v_ieee_summary #endif /* #if !defined(__VAXC) */ #else /* __OLD_STARLET */ union prdef { unsigned int pr$q_quad_access [2]; /* Access to register as a quadword */ unsigned int pr$l_long_access [2]; /* Access to register as a quadword */ __struct { unsigned pr$v_sid_sn : 12; /* SERIAL NUMBER FIELD */ unsigned pr$v_sid_pl : 3; /* PLANT ID */ unsigned pr$v_sid_eco : 9; /* ECO LEVEL */ unsigned pr$v_sid_type : 8; /* CPU TYPE CODE */ } pr$r_prdef_bits; __struct { unsigned pr$v_fill_xsid_bits : 24; /* CPU-SPECIFIC XSID BITS */ unsigned pr$v_xsid_type : 8; /* CPU SUBTYPE CODE */ } pr$r_prdef_xbits; /* SYSTEM ID REGISTER CPU TYPES */ /* Number assignments are */ /* based upon the jumpers */ /* read by the console from */ /* the MPS backplane */ /* ASTEN - AST Enabled Register */ /* */ /* NOTE WELL: These bit symbols are to be used only when interfacing to the */ /* ASTEN internal processor register. They are NOT to be used when */ /* interfacing to the copy of ASTEN which is stored in the Hardware */ /* Privileged Context Block (HWPCB). See the HWPCB-specific symbols */ /* for how to refer to the ASTEN field in the HWPCB. */ /* */ __union { unsigned pr$v_asten : 4; /* Enabled AST mask */ __struct { unsigned pr$v_asten_ken : 1; /* Kernel AST Enabled */ unsigned pr$v_asten_een : 1; /* Executive AST Enabled */ unsigned pr$v_asten_sen : 1; /* Supervisor AST Enabled */ unsigned pr$v_asten_uen : 1; /* User AST Enabled */ unsigned pr$v_fill_68_ : 4; } pr$r_asten_bits; } pr$r_asten_def; /* ASTSR - AST Summary Register */ /* */ /* NOTE WELL: These bit symbols are to be used only when interfacing to the */ /* ASTSR internal processor register. They are NOT to be used when */ /* interfacing to the copy of ASTSR which is stored in the Hardware */ /* Privileged Context Block (HWPCB). See the HWPCB-specific symbols */ /* for how to refer to the ASTSR field in the HWPCB. */ /* */ __union { unsigned pr$v_astsr : 4; /* AST pending summary mask */ __struct { unsigned pr$v_astsr_kpd : 1; /* Kernel AST Pending */ unsigned pr$v_astsr_epd : 1; /* Executive AST Pending */ unsigned pr$v_astsr_spd : 1; /* Supervisor AST Pending */ unsigned pr$v_astsr_upd : 1; /* User AST Pending */ unsigned pr$v_fill_69_ : 4; } pr$r_astsr_bits; } pr$r_astsr_def; /* FEN - Floating Point Enable */ /* */ /* NOTE WELL: These bit symbols are to be used only when interfacing to the */ /* FEN internal processor register. They are NOT to be used when */ /* interfacing to the copy of FEN which is stored in the Hardware */ /* Privileged Context Block (HWPCB). See the HWPCB-specific symbols */ /* for how to refer to the FEN field in the HWPCB. */ /* */ unsigned pr$v_fen_fen : 1; /* Floating point enabled = 1 */ /*------------------------------------------------------------------- */ /* DATFX - Data Alignment Trap Fixup */ /* */ unsigned pr$v_datfx_datfx : 1; /* Data Alignment Trap Fixup */ /*------------------------------------------------------------------- */ /* IPL - Interrupt Priority Level */ /* */ unsigned pr$v_ipl_ipl : 5; /* Interrupt Priority Level */ /*------------------------------------------------------------------- */ /* MCES - Machine Check Error Summary Register */ /* */ __struct { unsigned pr$v_mces_mck : 1; /* Machine Check (W1C) */ unsigned pr$v_mces_sce : 1; /* System Correctable Error (W1C) */ unsigned pr$v_mces_pce : 1; /* Processor Correctable Error (W1C) */ unsigned pr$v_mces_dpc : 1; /* Disable Processor Correctable Error report */ unsigned pr$v_mces_dsc : 1; /* Disable System Correctable Error report */ unsigned pr$v_fill_70_ : 3; } pr$r_mces_overlay; /*------------------------------------------------------------------- */ /* PCBB - Privileged Context Block Base */ /* */ /* PS - Processor Status */ /* */ /* The PS is not an IPR in the sense that it isn't read/written using */ /* the MxPR operators. However, the bitfields of the PS are defined */ /* here since this is the repository for bitfields of architected IPRs, */ /* hence it's convenient to define them here. */ /* */ /* Although the 'software' field of the PS is not privileged state and */ /* may be used by users as they see fit in User mode, VMS imposes a */ /* privileged interpretation on the bits when used in any of the three */ /* inner processor modes (Kernel, Executive, Supervisor). There are */ /* consequences of this: */ /* */ /* 1) Should User mode code be using the software field bits, it */ /* must be assumed that the User mode setting of these */ /* bits are entirely ignored by inner mode software. */ /* */ /* 2) VMS reserves the right to redefine its privileged (inner */ /* mode) interpretation of these bits at any time. */ /* */ __struct { unsigned pr$v_ps_sw : 2; /* Software Bits */ unsigned pr$v_fill_71_ : 6; } pr$r_ps_swdef_bits; __struct { unsigned pr$v_ps_prvmod : 2; /* Previous Processor Mode */ unsigned pr$v_ps_sysstate : 1; /* System State Indicator */ unsigned pr$v_ps_curmod : 2; /* Current Processor Mode */ unsigned psdef$$_ps_fill_1 : 2; unsigned pr$v_ps_vmm : 1; /* Virtual Machine Monitor */ unsigned pr$v_ps_ipl : 5; /* Interrupt Priority Level */ unsigned psdef$$_ps_fill_2 : 20; unsigned psdef$$_ps_fill_3 : 23; unsigned pr$v_ps_sp_align : 6; /* Stack Pointer Alignment */ unsigned pr$v_ps_mbz_62 : 1; /* Reserved bit above SP alignment */ unsigned pr$v_ps_mbz_63 : 1; /* Reserved bit above SP alignment */ } pr$r_psdef_bits; /* */ /* Maximum bit number used in the PS register */ /* */ /* MODE SYMBOL DEFINITIONS */ /* */ /* PTBR - Page Table Base Register */ /* */ unsigned pr$v_ptbr_pfn : 32; /* PFN of current L1PT */ /*------------------------------------------------------------------- */ /* SCBB - System Control Block Base */ /* */ unsigned pr$v_scbb_pfn : 32; /* PFN of SCB */ /*------------------------------------------------------------------- */ /* SIRR - Software Interrupt Request Register */ /* */ unsigned pr$v_sirr_lvl : 4; /* Software Interrupt Request Level */ /*------------------------------------------------------------------- */ /* SISR - Software Interrupt Summary Register */ /* */ __union { unsigned pr$v_sisr_summary : 16; /* Sofware Interrupt Summary */ __struct { unsigned pr$v_sisr_raz : 1; /* Read As Zero */ unsigned pr$v_sisr_ir1 : 1; /* Softint 1 pending */ unsigned pr$v_sisr_ir2 : 1; /* Softint 2 pending */ unsigned pr$v_sisr_ir3 : 1; /* Softint 3 pending */ unsigned pr$v_sisr_ir4 : 1; /* Softint 4 pending */ unsigned pr$v_sisr_ir5 : 1; /* Softint 5 pending */ unsigned pr$v_sisr_ir6 : 1; /* Softint 6 pending */ unsigned pr$v_sisr_ir7 : 1; /* Softint 7 pending */ unsigned pr$v_sisr_ir8 : 1; /* Softint 8 pending */ unsigned pr$v_sisr_ir9 : 1; /* Softint 9 pending */ unsigned pr$v_sisr_ir10 : 1; /* Softint 10 pending */ unsigned pr$v_sisr_ir11 : 1; /* Softint 11 pending */ unsigned pr$v_sisr_ir12 : 1; /* Softint 12 pending */ unsigned pr$v_sisr_ir13 : 1; /* Softint 13 pending */ unsigned pr$v_sisr_ir14 : 1; /* Softint 14 pending */ unsigned pr$v_sisr_ir15 : 1; /* Softint 15 pending */ } pr$r_sisr_bits; } pr$r_sisr_fields; /*------------------------------------------------------------------- */ /* TBCHK - Translation Buffer Check */ /* */ /* This IPR may always be referenced with MFPR without causing an error */ /* to occur (unlike VAX), but the feature provided by TBCHK may or may */ /* not be implemented. If not, then =1 and */ /* should be ignored. If TBCHK's function IS implemented, then */ /* =0 and returns the desired data. */ /* */ __struct { unsigned pr$v_tbchk_va_present : 1; /* VA in TB = 1 */ unsigned pr$v_fill_1 : 31; unsigned pr$v_fill_2 : 31; unsigned pr$v_tbchk_no_tbchk : 1; /* Not implemented = 1 */ } pr$r_tbchk_bits; /*------------------------------------------------------------------- */ /* FPCR - Floating Point Control Register */ /* */ /* NOTE WELL: These bit symbols are to be used only when interfacing to the */ /* hardware FPCR internal processor register. They are NOT to be used when */ /* interfacing to the software floating point control register pointed to */ /* by CTL$GQ_IEEE_FP_CONTROL/PKTA$Q_IEEE_FP_CONTROL. */ /* */ /* The hardware FPCR should only be manipulated via the system service, */ /* SYS$IEEE_FP_CONTROL, rather than directly. */ /* */ __struct { unsigned pr$v_fpcr_fill_1 : 32; unsigned pr$v_fpcr_fill_2 : 15; unsigned pr$v_ieee_dnod : 1; /* Denormal operand exception disable */ unsigned pr$v_ieee_dnz : 1; /* Denormal operands to 0.0 */ unsigned pr$v_ieee_invd : 1; /* Invalid operation disable */ unsigned pr$v_ieee_dzed : 1; /* Division by zero disable */ unsigned pr$v_ieee_ovfd : 1; /* Overflow disable */ unsigned pr$v_ieee_inv : 1; /* Invalid operation. */ unsigned pr$v_ieee_dze : 1; /* Division by zero occured. */ unsigned pr$v_ieee_ovf : 1; /* Overflow occured. */ unsigned pr$v_ieee_unf : 1; /* Underflow occured. */ unsigned pr$v_ieee_ine : 1; /* Inexact result occured. */ unsigned pr$v_ieee_iov : 1; /* Integer overflow occured */ unsigned pr$v_ieee_dyn_rnd : 2; /* Dynamic Rounding mode */ unsigned pr$v_ieee_undz : 1; /* Underflow to zero */ unsigned pr$v_ieee_unfd : 1; /* Underflow disable */ unsigned pr$v_ieee_ined : 1; /* Inexact disable */ unsigned pr$v_ieee_summary : 1; /* Bitwise OR of FPCR exception bits */ } pr$r_fpcr_bits; } ; #if !defined(__VAXC) #define pr$v_sid_sn pr$r_prdef_bits.pr$v_sid_sn #define pr$v_sid_pl pr$r_prdef_bits.pr$v_sid_pl #define pr$v_sid_eco pr$r_prdef_bits.pr$v_sid_eco #define pr$v_sid_type pr$r_prdef_bits.pr$v_sid_type #define pr$v_xsid_type pr$r_prdef_xbits.pr$v_xsid_type #define pr$v_asten pr$r_asten_def.pr$v_asten #define pr$v_asten_ken pr$r_asten_def.pr$r_asten_bits.pr$v_asten_ken #define pr$v_asten_een pr$r_asten_def.pr$r_asten_bits.pr$v_asten_een #define pr$v_asten_sen pr$r_asten_def.pr$r_asten_bits.pr$v_asten_sen #define pr$v_asten_uen pr$r_asten_def.pr$r_asten_bits.pr$v_asten_uen #define pr$v_astsr pr$r_astsr_def.pr$v_astsr #define pr$v_astsr_kpd pr$r_astsr_def.pr$r_astsr_bits.pr$v_astsr_kpd #define pr$v_astsr_epd pr$r_astsr_def.pr$r_astsr_bits.pr$v_astsr_epd #define pr$v_astsr_spd pr$r_astsr_def.pr$r_astsr_bits.pr$v_astsr_spd #define pr$v_astsr_upd pr$r_astsr_def.pr$r_astsr_bits.pr$v_astsr_upd #define pr$v_mces_mck pr$r_mces_overlay.pr$v_mces_mck #define pr$v_mces_sce pr$r_mces_overlay.pr$v_mces_sce #define pr$v_mces_pce pr$r_mces_overlay.pr$v_mces_pce #define pr$v_mces_dpc pr$r_mces_overlay.pr$v_mces_dpc #define pr$v_mces_dsc pr$r_mces_overlay.pr$v_mces_dsc #define pr$v_ps_sw pr$r_ps_swdef_bits.pr$v_ps_sw #define pr$v_ps_prvmod pr$r_psdef_bits.pr$v_ps_prvmod #define pr$v_ps_sysstate pr$r_psdef_bits.pr$v_ps_sysstate #define pr$v_ps_curmod pr$r_psdef_bits.pr$v_ps_curmod #define pr$v_ps_vmm pr$r_psdef_bits.pr$v_ps_vmm #define pr$v_ps_ipl pr$r_psdef_bits.pr$v_ps_ipl #define pr$v_ps_sp_align pr$r_psdef_bits.pr$v_ps_sp_align #define pr$v_ps_mbz_62 pr$r_psdef_bits.pr$v_ps_mbz_62 #define pr$v_ps_mbz_63 pr$r_psdef_bits.pr$v_ps_mbz_63 #define pr$v_sisr_summary pr$r_sisr_fields.pr$v_sisr_summary #define pr$v_sisr_ir1 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir1 #define pr$v_sisr_ir2 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir2 #define pr$v_sisr_ir3 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir3 #define pr$v_sisr_ir4 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir4 #define pr$v_sisr_ir5 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir5 #define pr$v_sisr_ir6 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir6 #define pr$v_sisr_ir7 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir7 #define pr$v_sisr_ir8 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir8 #define pr$v_sisr_ir9 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir9 #define pr$v_sisr_ir10 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir10 #define pr$v_sisr_ir11 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir11 #define pr$v_sisr_ir12 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir12 #define pr$v_sisr_ir13 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir13 #define pr$v_sisr_ir14 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir14 #define pr$v_sisr_ir15 pr$r_sisr_fields.pr$r_sisr_bits.pr$v_sisr_ir15 #define pr$v_tbchk_va_present pr$r_tbchk_bits.pr$v_tbchk_va_present #define pr$v_tbchk_no_tbchk pr$r_tbchk_bits.pr$v_tbchk_no_tbchk #define pr$v_ieee_dnod pr$r_fpcr_bits.pr$v_ieee_dnod #define pr$v_ieee_dnz pr$r_fpcr_bits.pr$v_ieee_dnz #define pr$v_ieee_invd pr$r_fpcr_bits.pr$v_ieee_invd #define pr$v_ieee_dzed pr$r_fpcr_bits.pr$v_ieee_dzed #define pr$v_ieee_ovfd pr$r_fpcr_bits.pr$v_ieee_ovfd #define pr$v_ieee_inv pr$r_fpcr_bits.pr$v_ieee_inv #define pr$v_ieee_dze pr$r_fpcr_bits.pr$v_ieee_dze #define pr$v_ieee_ovf pr$r_fpcr_bits.pr$v_ieee_ovf #define pr$v_ieee_unf pr$r_fpcr_bits.pr$v_ieee_unf #define pr$v_ieee_ine pr$r_fpcr_bits.pr$v_ieee_ine #define pr$v_ieee_iov pr$r_fpcr_bits.pr$v_ieee_iov #define pr$v_ieee_dyn_rnd pr$r_fpcr_bits.pr$v_ieee_dyn_rnd #define pr$v_ieee_undz pr$r_fpcr_bits.pr$v_ieee_undz #define pr$v_ieee_unfd pr$r_fpcr_bits.pr$v_ieee_unfd #define pr$v_ieee_ined pr$r_fpcr_bits.pr$v_ieee_ined #define pr$v_ieee_summary pr$r_fpcr_bits.pr$v_ieee_summary #endif /* #if !defined(__VAXC) */ #endif /* #ifdef __NEW_STARLET */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __PRDEF_LOADED */ /* CC header ends here */ #endif /* IAS_ASSEMBLER */