/********************************************************************************************************************************/ /* Created: 9-Mar-2021 22:28:05 by OpenVMS SDL EV3-3 */ /* Source: 09-MAR-2021 22:28:01 $1$DGA8085:[STARLET_H.SRC]STARDEFAE.SDI;1 */ /********************************************************************************************************************************/ /*** MODULE $DEVDEF ***/ #ifndef __DEVDEF_LOADED #define __DEVDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /* */ /* THE FOLLOWING BITS DEFINE THE DEVICE CHARACTERISTICS FOR */ /* BOTH THE UCBS AND RMS. */ /* */ #define DEV$M_REC 0x1 #define DEV$M_CCL 0x2 #define DEV$M_TRM 0x4 #define DEV$M_DIR 0x8 #define DEV$M_SDI 0x10 #define DEV$M_SQD 0x20 #define DEV$M_SPL 0x40 #define DEV$M_OPR 0x80 #define DEV$M_RCT 0x100 #define DEV$M_QSVD 0x200 #define DEV$M_QSVBL 0x400 #define DEV$M_MPDEV_SECONDARY 0x800 #define DEV$M_MPDEV_MEMBER 0x1000 #define DEV$M_NET 0x2000 #define DEV$M_FOD 0x4000 #define DEV$M_DUA 0x8000 #define DEV$M_SHR 0x10000 #define DEV$M_GEN 0x20000 #define DEV$M_AVL 0x40000 #define DEV$M_MNT 0x80000 #define DEV$M_MBX 0x100000 #define DEV$M_DMT 0x200000 #define DEV$M_ELG 0x400000 #define DEV$M_ALL 0x800000 #define DEV$M_FOR 0x1000000 #define DEV$M_SWL 0x2000000 #define DEV$M_IDV 0x4000000 #define DEV$M_ODV 0x8000000 #define DEV$M_RND 0x10000000 #define DEV$M_RTM 0x20000000 #define DEV$M_RCK 0x40000000 #define DEV$M_WCK 0x80000000 #define DEV$M_CLU 0x1 #define DEV$M_DET 0x2 #define DEV$M_RTT 0x4 #define DEV$M_CDP 0x8 #define DEV$M_2P 0x10 #define DEV$M_MSCP 0x20 #define DEV$M_SSM 0x40 #define DEV$M_SRV 0x80 #define DEV$M_RED 0x100 #define DEV$M_NNM 0x200 #define DEV$M_WBC 0x400 #define DEV$M_WTC 0x800 #define DEV$M_HOC 0x1000 #define DEV$M_LOC 0x2000 #define DEV$M_DFS 0x4000 #define DEV$M_DAP 0x8000 #define DEV$M_NLT 0x10000 #define DEV$M_SEX 0x20000 #define DEV$M_SHD 0x40000 #define DEV$M_VRT 0x80000 #define DEV$M_LDR 0x100000 #define DEV$M_NOLB 0x200000 #define DEV$M_NOCLU 0x400000 #define DEV$M_VMEM 0x800000 #define DEV$M_SCSI 0x1000000 #define DEV$M_WLG 0x2000000 #define DEV$M_NOFE 0x4000000 #define DEV$M_FILL_2 0x8000000 #define DEV$M_CRAMIO 0x10000000 #define DEV$M_DTN 0x20000000 #define DEV$M_FILL_3 0x40000000 #define DEV$M_POOL_MBR 0x80000000 #ifdef __NEW_STARLET typedef union _devdef { __struct { unsigned dev$v_rec : 1; /* DEVICE RECORD ORIENTED */ unsigned dev$v_ccl : 1; /* CARRIAGE CONTROL DEVICE */ unsigned dev$v_trm : 1; /* DEVICE IS A TERMINAL */ unsigned dev$v_dir : 1; /* DEVICE IS DIRECTORY STRUCTURED */ unsigned dev$v_sdi : 1; /* DEVICE IS SINGLE DIRECTORY STRUCTURED */ unsigned dev$v_sqd : 1; /* SEQUENTIAL BLOCK-ORIENTED DEVICE (I.E., MAGTAPE) */ unsigned dev$v_spl : 1; /* DEVICE BEING SPOOLED */ unsigned dev$v_opr : 1; /* DEVICE IS AN OPERATOR */ unsigned dev$v_rct : 1; /* DISK CONTAINS RCT (DEC STANDARD 166 DISK) */ unsigned dev$v_qsvd : 1; /* Client device is served by QIOserver */ unsigned dev$v_qsvbl : 1; /* Server device is servable by QIOserver */ unsigned dev$v_mpdev_secondary : 1; /* Indicates secondary unit in a multipath set */ unsigned dev$v_mpdev_member : 1; /* Device is part of a multipath set. */ unsigned dev$v_net : 1; /* NETWORK DEVICE */ unsigned dev$v_fod : 1; /* FILES-ORIENTED DEVICE (I.E., DISK AND MT) */ unsigned dev$v_dua : 1; /* DEVICE IS DUAL PORTED */ unsigned dev$v_shr : 1; /* DEVICE SHAREABLE */ unsigned dev$v_gen : 1; /* DEVICE IS A GENERIC DEVICE */ unsigned dev$v_avl : 1; /* DEVICE AVAILABLE FOR USE */ unsigned dev$v_mnt : 1; /* DEVICE IS MOUNTED */ unsigned dev$v_mbx : 1; /* DEVICE IS A MAILBOX */ unsigned dev$v_dmt : 1; /* DEVICE MARKED FOR DISMOUNT */ unsigned dev$v_elg : 1; /* DEVICE HAS ERROR LOGGING ENABLED */ unsigned dev$v_all : 1; /* DEVICE IS ALLOCATED */ unsigned dev$v_for : 1; /* DEVICE IS MOUNTED FOREIGN (I.E., NON-FILE STRUCTURED) */ unsigned dev$v_swl : 1; /* DEVICE IS SOFTWARE WRITE LOCKED */ unsigned dev$v_idv : 1; /* DEVICE CAPABLE OF PROVIDING INPUT */ unsigned dev$v_odv : 1; /* DEVICE CAPABLE OF PROVIDING OUTPUT */ unsigned dev$v_rnd : 1; /* DEVICE ALLOWS RANDOM ACCESS */ unsigned dev$v_rtm : 1; /* DEVICE IS REALTIME IN NATURE */ unsigned dev$v_rck : 1; /* DEVICE HAS READ CHECKING ENABLED */ unsigned dev$v_wck : 1; /* DEVICE HAS WRITE CHECKING ENABLED */ } dev$r_devdef_bits0; __struct { unsigned dev$v_clu : 1; /* DEVICE IS AVAILABLE CLUSTER-WIDE */ unsigned dev$v_det : 1; /* DEVICE IS DETACHED TERMINAL */ unsigned dev$v_rtt : 1; /* DEVICE HAS REMOTE TERMINAL UCB EXTENSION */ unsigned dev$v_cdp : 1; /* DUAL PATH DEVICE WITH 2 UCBs */ unsigned dev$v_2p : 1; /* TWO PATHS ARE KNOWN TO THIS DEVICE */ unsigned dev$v_mscp : 1; /* DEVICE ACCESSED USING MSCP (disk or tape) */ unsigned dev$v_ssm : 1; /* this bit was set for Phase I (controller-based) */ /* shadowing only. This bit is not set for */ /* Phase II (host-based) shadowing; Phase II */ /* sets the SHD bit (see below). */ unsigned dev$v_srv : 1; /* DEVICE IS SERVED VIA THE MSCP SERVER */ unsigned dev$v_red : 1; /* DEVICE IS redirected terminal */ unsigned dev$v_nnm : 1; /* DEVICE HAS "node$" PREFIX */ unsigned dev$v_wbc : 1; /* DEVICE SUPPORTS WRITE-BACK CACHING */ unsigned dev$v_wtc : 1; /* DEVICE SUPPORTS WRITE-THROUGH CACHING */ unsigned dev$v_hoc : 1; /* DEVICE SUPPORTS HOST CACHING */ unsigned dev$v_loc : 1; /* DEVICE ACCESSIBLE VIA LOCAL (NON-EMULATED) CONTROLLER */ unsigned dev$v_dfs : 1; /* DEVICE IS DFS-SERVED */ unsigned dev$v_dap : 1; /* DEVICE IS DAP ACCESSED */ unsigned dev$v_nlt : 1; /* DEVICE IS NOT-LAST-TRACK (I.E. IT HAS NO BAD BLOCK */ /* INFORMATION ON ITS LAST TRACK) */ unsigned dev$v_sex : 1; /* DEVICE (tape) SUPPORTS SERIOUS EXCEPTION HANDLING */ unsigned dev$v_shd : 1; /* DEVICE IS A MEMBER OF A HOST BASED SHADOW SET */ unsigned dev$v_vrt : 1; /* DEVICE IS A SHADOW SET VIRTUAL UNIT */ unsigned dev$v_ldr : 1; /* LOADER PRESENT (TAPES) */ unsigned dev$v_nolb : 1; /* DEVICE IGNORES SERVER LOAD BALANCING REQUESTS */ unsigned dev$v_noclu : 1; /* DEVICE WILL NEVER BE AVAILABLE CLUSTER-WIDE */ unsigned dev$v_vmem : 1; /* Virtual member of a constituent set */ unsigned dev$v_scsi : 1; /* DEVICE IS A SCSI DEVICE */ unsigned dev$v_wlg : 1; /* DEVICE HAS MSCP Based (Phase I) WRITE LOGGING CAPABILITY */ unsigned dev$v_nofe : 1; /* DEVICE DOESN'T SUPPORT FORCED ERROR */ unsigned dev$v_fill_2 : 1; /* Reserved for: Allocation in progress (MME) */ unsigned dev$v_cramio : 1; /* Performs Mailbox I/O */ unsigned dev$v_dtn : 1; /* Device has DDR Device Type Name available */ unsigned dev$v_fill_3 : 1; unsigned dev$v_pool_mbr : 1; /* Unit is bound to a storage pool */ } dev$r_devdef_bits1; } DEVDEF; #if !defined(__VAXC) #define dev$v_rec dev$r_devdef_bits0.dev$v_rec #define dev$v_ccl dev$r_devdef_bits0.dev$v_ccl #define dev$v_trm dev$r_devdef_bits0.dev$v_trm #define dev$v_dir dev$r_devdef_bits0.dev$v_dir #define dev$v_sdi dev$r_devdef_bits0.dev$v_sdi #define dev$v_sqd dev$r_devdef_bits0.dev$v_sqd #define dev$v_spl dev$r_devdef_bits0.dev$v_spl #define dev$v_opr dev$r_devdef_bits0.dev$v_opr #define dev$v_rct dev$r_devdef_bits0.dev$v_rct #define dev$v_qsvd dev$r_devdef_bits0.dev$v_qsvd #define dev$v_qsvbl dev$r_devdef_bits0.dev$v_qsvbl #define dev$v_mpdev_secondary dev$r_devdef_bits0.dev$v_mpdev_secondary #define dev$v_mpdev_member dev$r_devdef_bits0.dev$v_mpdev_member #define dev$v_net dev$r_devdef_bits0.dev$v_net #define dev$v_fod dev$r_devdef_bits0.dev$v_fod #define dev$v_dua dev$r_devdef_bits0.dev$v_dua #define dev$v_shr dev$r_devdef_bits0.dev$v_shr #define dev$v_gen dev$r_devdef_bits0.dev$v_gen #define dev$v_avl dev$r_devdef_bits0.dev$v_avl #define dev$v_mnt dev$r_devdef_bits0.dev$v_mnt #define dev$v_mbx dev$r_devdef_bits0.dev$v_mbx #define dev$v_dmt dev$r_devdef_bits0.dev$v_dmt #define dev$v_elg dev$r_devdef_bits0.dev$v_elg #define dev$v_all dev$r_devdef_bits0.dev$v_all #define dev$v_for dev$r_devdef_bits0.dev$v_for #define dev$v_swl dev$r_devdef_bits0.dev$v_swl #define dev$v_idv dev$r_devdef_bits0.dev$v_idv #define dev$v_odv dev$r_devdef_bits0.dev$v_odv #define dev$v_rnd dev$r_devdef_bits0.dev$v_rnd #define dev$v_rtm dev$r_devdef_bits0.dev$v_rtm #define dev$v_rck dev$r_devdef_bits0.dev$v_rck #define dev$v_wck dev$r_devdef_bits0.dev$v_wck #define dev$v_clu dev$r_devdef_bits1.dev$v_clu #define dev$v_det dev$r_devdef_bits1.dev$v_det #define dev$v_rtt dev$r_devdef_bits1.dev$v_rtt #define dev$v_cdp dev$r_devdef_bits1.dev$v_cdp #define dev$v_2p dev$r_devdef_bits1.dev$v_2p #define dev$v_mscp dev$r_devdef_bits1.dev$v_mscp #define dev$v_ssm dev$r_devdef_bits1.dev$v_ssm #define dev$v_srv dev$r_devdef_bits1.dev$v_srv #define dev$v_red dev$r_devdef_bits1.dev$v_red #define dev$v_nnm dev$r_devdef_bits1.dev$v_nnm #define dev$v_wbc dev$r_devdef_bits1.dev$v_wbc #define dev$v_wtc dev$r_devdef_bits1.dev$v_wtc #define dev$v_hoc dev$r_devdef_bits1.dev$v_hoc #define dev$v_loc dev$r_devdef_bits1.dev$v_loc #define dev$v_dfs dev$r_devdef_bits1.dev$v_dfs #define dev$v_dap dev$r_devdef_bits1.dev$v_dap #define dev$v_nlt dev$r_devdef_bits1.dev$v_nlt #define dev$v_sex dev$r_devdef_bits1.dev$v_sex #define dev$v_shd dev$r_devdef_bits1.dev$v_shd #define dev$v_vrt dev$r_devdef_bits1.dev$v_vrt #define dev$v_ldr dev$r_devdef_bits1.dev$v_ldr #define dev$v_nolb dev$r_devdef_bits1.dev$v_nolb #define dev$v_noclu dev$r_devdef_bits1.dev$v_noclu #define dev$v_vmem dev$r_devdef_bits1.dev$v_vmem #define dev$v_scsi dev$r_devdef_bits1.dev$v_scsi #define dev$v_wlg dev$r_devdef_bits1.dev$v_wlg #define dev$v_nofe dev$r_devdef_bits1.dev$v_nofe #define dev$v_fill_2 dev$r_devdef_bits1.dev$v_fill_2 #define dev$v_cramio dev$r_devdef_bits1.dev$v_cramio #define dev$v_dtn dev$r_devdef_bits1.dev$v_dtn #define dev$v_pool_mbr dev$r_devdef_bits1.dev$v_pool_mbr #endif /* #if !defined(__VAXC) */ #else /* __OLD_STARLET */ union devdef { __struct { unsigned dev$v_rec : 1; /* DEVICE RECORD ORIENTED */ unsigned dev$v_ccl : 1; /* CARRIAGE CONTROL DEVICE */ unsigned dev$v_trm : 1; /* DEVICE IS A TERMINAL */ unsigned dev$v_dir : 1; /* DEVICE IS DIRECTORY STRUCTURED */ unsigned dev$v_sdi : 1; /* DEVICE IS SINGLE DIRECTORY STRUCTURED */ unsigned dev$v_sqd : 1; /* SEQUENTIAL BLOCK-ORIENTED DEVICE (I.E., MAGTAPE) */ unsigned dev$v_spl : 1; /* DEVICE BEING SPOOLED */ unsigned dev$v_opr : 1; /* DEVICE IS AN OPERATOR */ unsigned dev$v_rct : 1; /* DISK CONTAINS RCT (DEC STANDARD 166 DISK) */ unsigned dev$v_qsvd : 1; /* Client device is served by QIOserver */ unsigned dev$v_qsvbl : 1; /* Server device is servable by QIOserver */ unsigned dev$v_mpdev_secondary : 1; /* Indicates secondary unit in a multipath set */ unsigned dev$v_mpdev_member : 1; /* Device is part of a multipath set. */ unsigned dev$v_net : 1; /* NETWORK DEVICE */ unsigned dev$v_fod : 1; /* FILES-ORIENTED DEVICE (I.E., DISK AND MT) */ unsigned dev$v_dua : 1; /* DEVICE IS DUAL PORTED */ unsigned dev$v_shr : 1; /* DEVICE SHAREABLE */ unsigned dev$v_gen : 1; /* DEVICE IS A GENERIC DEVICE */ unsigned dev$v_avl : 1; /* DEVICE AVAILABLE FOR USE */ unsigned dev$v_mnt : 1; /* DEVICE IS MOUNTED */ unsigned dev$v_mbx : 1; /* DEVICE IS A MAILBOX */ unsigned dev$v_dmt : 1; /* DEVICE MARKED FOR DISMOUNT */ unsigned dev$v_elg : 1; /* DEVICE HAS ERROR LOGGING ENABLED */ unsigned dev$v_all : 1; /* DEVICE IS ALLOCATED */ unsigned dev$v_for : 1; /* DEVICE IS MOUNTED FOREIGN (I.E., NON-FILE STRUCTURED) */ unsigned dev$v_swl : 1; /* DEVICE IS SOFTWARE WRITE LOCKED */ unsigned dev$v_idv : 1; /* DEVICE CAPABLE OF PROVIDING INPUT */ unsigned dev$v_odv : 1; /* DEVICE CAPABLE OF PROVIDING OUTPUT */ unsigned dev$v_rnd : 1; /* DEVICE ALLOWS RANDOM ACCESS */ unsigned dev$v_rtm : 1; /* DEVICE IS REALTIME IN NATURE */ unsigned dev$v_rck : 1; /* DEVICE HAS READ CHECKING ENABLED */ unsigned dev$v_wck : 1; /* DEVICE HAS WRITE CHECKING ENABLED */ } dev$r_devdef_bits0; __struct { unsigned dev$v_clu : 1; /* DEVICE IS AVAILABLE CLUSTER-WIDE */ unsigned dev$v_det : 1; /* DEVICE IS DETACHED TERMINAL */ unsigned dev$v_rtt : 1; /* DEVICE HAS REMOTE TERMINAL UCB EXTENSION */ unsigned dev$v_cdp : 1; /* DUAL PATH DEVICE WITH 2 UCBs */ unsigned dev$v_2p : 1; /* TWO PATHS ARE KNOWN TO THIS DEVICE */ unsigned dev$v_mscp : 1; /* DEVICE ACCESSED USING MSCP (disk or tape) */ unsigned dev$v_ssm : 1; /* this bit was set for Phase I (controller-based) */ /* shadowing only. This bit is not set for */ /* Phase II (host-based) shadowing; Phase II */ /* sets the SHD bit (see below). */ unsigned dev$v_srv : 1; /* DEVICE IS SERVED VIA THE MSCP SERVER */ unsigned dev$v_red : 1; /* DEVICE IS redirected terminal */ unsigned dev$v_nnm : 1; /* DEVICE HAS "node$" PREFIX */ unsigned dev$v_wbc : 1; /* DEVICE SUPPORTS WRITE-BACK CACHING */ unsigned dev$v_wtc : 1; /* DEVICE SUPPORTS WRITE-THROUGH CACHING */ unsigned dev$v_hoc : 1; /* DEVICE SUPPORTS HOST CACHING */ unsigned dev$v_loc : 1; /* DEVICE ACCESSIBLE VIA LOCAL (NON-EMULATED) CONTROLLER */ unsigned dev$v_dfs : 1; /* DEVICE IS DFS-SERVED */ unsigned dev$v_dap : 1; /* DEVICE IS DAP ACCESSED */ unsigned dev$v_nlt : 1; /* DEVICE IS NOT-LAST-TRACK (I.E. IT HAS NO BAD BLOCK */ /* INFORMATION ON ITS LAST TRACK) */ unsigned dev$v_sex : 1; /* DEVICE (tape) SUPPORTS SERIOUS EXCEPTION HANDLING */ unsigned dev$v_shd : 1; /* DEVICE IS A MEMBER OF A HOST BASED SHADOW SET */ unsigned dev$v_vrt : 1; /* DEVICE IS A SHADOW SET VIRTUAL UNIT */ unsigned dev$v_ldr : 1; /* LOADER PRESENT (TAPES) */ unsigned dev$v_nolb : 1; /* DEVICE IGNORES SERVER LOAD BALANCING REQUESTS */ unsigned dev$v_noclu : 1; /* DEVICE WILL NEVER BE AVAILABLE CLUSTER-WIDE */ unsigned dev$v_vmem : 1; /* Virtual member of a constituent set */ unsigned dev$v_scsi : 1; /* DEVICE IS A SCSI DEVICE */ unsigned dev$v_wlg : 1; /* DEVICE HAS MSCP Based (Phase I) WRITE LOGGING CAPABILITY */ unsigned dev$v_nofe : 1; /* DEVICE DOESN'T SUPPORT FORCED ERROR */ unsigned dev$v_fill_2 : 1; /* Reserved for: Allocation in progress (MME) */ unsigned dev$v_cramio : 1; /* Performs Mailbox I/O */ unsigned dev$v_dtn : 1; /* Device has DDR Device Type Name available */ unsigned dev$v_fill_3 : 1; unsigned dev$v_pool_mbr : 1; /* Unit is bound to a storage pool */ } dev$r_devdef_bits1; } ; #if !defined(__VAXC) #define dev$v_rec dev$r_devdef_bits0.dev$v_rec #define dev$v_ccl dev$r_devdef_bits0.dev$v_ccl #define dev$v_trm dev$r_devdef_bits0.dev$v_trm #define dev$v_dir dev$r_devdef_bits0.dev$v_dir #define dev$v_sdi dev$r_devdef_bits0.dev$v_sdi #define dev$v_sqd dev$r_devdef_bits0.dev$v_sqd #define dev$v_spl dev$r_devdef_bits0.dev$v_spl #define dev$v_opr dev$r_devdef_bits0.dev$v_opr #define dev$v_rct dev$r_devdef_bits0.dev$v_rct #define dev$v_qsvd dev$r_devdef_bits0.dev$v_qsvd #define dev$v_qsvbl dev$r_devdef_bits0.dev$v_qsvbl #define dev$v_mpdev_secondary dev$r_devdef_bits0.dev$v_mpdev_secondary #define dev$v_mpdev_member dev$r_devdef_bits0.dev$v_mpdev_member #define dev$v_net dev$r_devdef_bits0.dev$v_net #define dev$v_fod dev$r_devdef_bits0.dev$v_fod #define dev$v_dua dev$r_devdef_bits0.dev$v_dua #define dev$v_shr dev$r_devdef_bits0.dev$v_shr #define dev$v_gen dev$r_devdef_bits0.dev$v_gen #define dev$v_avl dev$r_devdef_bits0.dev$v_avl #define dev$v_mnt dev$r_devdef_bits0.dev$v_mnt #define dev$v_mbx dev$r_devdef_bits0.dev$v_mbx #define dev$v_dmt dev$r_devdef_bits0.dev$v_dmt #define dev$v_elg dev$r_devdef_bits0.dev$v_elg #define dev$v_all dev$r_devdef_bits0.dev$v_all #define dev$v_for dev$r_devdef_bits0.dev$v_for #define dev$v_swl dev$r_devdef_bits0.dev$v_swl #define dev$v_idv dev$r_devdef_bits0.dev$v_idv #define dev$v_odv dev$r_devdef_bits0.dev$v_odv #define dev$v_rnd dev$r_devdef_bits0.dev$v_rnd #define dev$v_rtm dev$r_devdef_bits0.dev$v_rtm #define dev$v_rck dev$r_devdef_bits0.dev$v_rck #define dev$v_wck dev$r_devdef_bits0.dev$v_wck #define dev$v_clu dev$r_devdef_bits1.dev$v_clu #define dev$v_det dev$r_devdef_bits1.dev$v_det #define dev$v_rtt dev$r_devdef_bits1.dev$v_rtt #define dev$v_cdp dev$r_devdef_bits1.dev$v_cdp #define dev$v_2p dev$r_devdef_bits1.dev$v_2p #define dev$v_mscp dev$r_devdef_bits1.dev$v_mscp #define dev$v_ssm dev$r_devdef_bits1.dev$v_ssm #define dev$v_srv dev$r_devdef_bits1.dev$v_srv #define dev$v_red dev$r_devdef_bits1.dev$v_red #define dev$v_nnm dev$r_devdef_bits1.dev$v_nnm #define dev$v_wbc dev$r_devdef_bits1.dev$v_wbc #define dev$v_wtc dev$r_devdef_bits1.dev$v_wtc #define dev$v_hoc dev$r_devdef_bits1.dev$v_hoc #define dev$v_loc dev$r_devdef_bits1.dev$v_loc #define dev$v_dfs dev$r_devdef_bits1.dev$v_dfs #define dev$v_dap dev$r_devdef_bits1.dev$v_dap #define dev$v_nlt dev$r_devdef_bits1.dev$v_nlt #define dev$v_sex dev$r_devdef_bits1.dev$v_sex #define dev$v_shd dev$r_devdef_bits1.dev$v_shd #define dev$v_vrt dev$r_devdef_bits1.dev$v_vrt #define dev$v_ldr dev$r_devdef_bits1.dev$v_ldr #define dev$v_nolb dev$r_devdef_bits1.dev$v_nolb #define dev$v_noclu dev$r_devdef_bits1.dev$v_noclu #define dev$v_vmem dev$r_devdef_bits1.dev$v_vmem #define dev$v_scsi dev$r_devdef_bits1.dev$v_scsi #define dev$v_wlg dev$r_devdef_bits1.dev$v_wlg #define dev$v_nofe dev$r_devdef_bits1.dev$v_nofe #define dev$v_fill_2 dev$r_devdef_bits1.dev$v_fill_2 #define dev$v_cramio dev$r_devdef_bits1.dev$v_cramio #define dev$v_dtn dev$r_devdef_bits1.dev$v_dtn #define dev$v_pool_mbr dev$r_devdef_bits1.dev$v_pool_mbr #endif /* #if !defined(__VAXC) */ #endif /* #ifdef __NEW_STARLET */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __DEVDEF_LOADED */