OpenVMS Alpha only

  Specifies the lowest version of  the  Alpha  architecture  where
  this  code  will  run,  which can allow the compiler to generate
  more efficient code, with the tradeoff that code may not run  on
  older systems, unlike the /OPTIMIZE=TUNE qualifier.

  All Alpha processors implement a core set of  instructions  and,
  in  some  cases, the following extensions:  BWX (byte- and word-
  manipulation  instructions),  MAX   (multimedia   instructions),
  square   root   instruction,   integer/floating-point   register
  transfer  instructions,  additional  instructions  to   identify
  extensions  and  processor  groups,  and bit count instructions.
  (The  Alpha  Architecture   Reference   Manual   describes   the
  extensions in detail.)

  The value specified on /ARCHITECTURE becomes the  default  value
  for the /OPTIMIZE=TUNE qualifier.

  The  keyword  specified   with   the   /ARCHITECTURE   qualifier
  determines  which  instructions  the  compiler can generate, and
  which coding rules it must follow:

     GENERIC
       Generate instructions that are appropriate for all Alpha
       processors. This option is the default, and is equivalent to
       /ARCH=EV4.

     HOST
       Generate instructions for the processor that the compiler is
       running on (for example, EV56 instructions on an EV56 processor,
       EV4 instructions on an EV4 processor, and so on).

     EV4
       Generate instructions for the EV4 processor (21064, 20164A,
       21066, and 21068 chips).

       Applications compiled with this option will not incur any
       emulation overhead on any Alpha processor.

     EV5
       Generate instructions for the EV5 processor (some 21164 chips).
       (Note that the EV5 and EV56 processors both have the same chip
       number - 21164.)

       Applications compiled with this option will not incur any
       emulation overhead on any Alpha processor.

     EV56
       Generate instructions for EV56 processors (some 21164 chips).

       This option permits the compiler to generate any EV4 instruction,
       plus any instructions contained in the BWX extension.

       Applications compiled with this option may incur emulation
       overhead on EV4 and EV5 processors.

     PCA56
       Generate instructions for PCA56 processors (21164PC chips).

       This option permits the compiler to generate any EV4 instruction,
       plus any instructions contained in the BWX and MAX extensions.
       However, HP Pascal does not generate any of the instructions in
       the MAX (multimedia) extension to the Alpha architecture.

       Applications compiled with this option may incur emulation
       overhead on EV4 and EV5 processors.

     EV6
       Generate instructions for EV6 processors (21264 chips).

       This option permits the compiler to generate any EV4 instruction,
       any instruction contained in the BWX and MAX extensions, plus
       any instructions added for the EV6 chip.  These new instructions
       include a floating-point square root instruction (SQRT),
       integer/floating-point register transfer instructions, and
       additional instructions to identify extensions and processor groups.

       Applications compiled with this option may incur emulation
       overhead on EV4, EV5, EV56, and PCA56 processors.

     EV67
     EV68
       Generate instructions for EV67 and EV68 processors (21264A chips).

       This option permits the compiler to generate any EV6 instruction,
       plus the new bit count instructions (CTLZ, CTPOP, and CTTZ).
       However, HP Pascal does not currently generate any of the
       new bit count instructions and the EV67 and EV68 have identical
       instruction scheduling models so the EV67 and EV68 are essentially
       identical to the EV6.

       However, HP Pascal does not currently generate any of the
       new bit count instructions so EV67 is essentially identical to EV6.

       Applications compiled with this option may incur emulation
       overhead on EV4, EV5, EV56, and PCA56 processors.

     EV7
       Generate instructions for the EV7 processor (21364 chip).

       This option permits the compiler to generate any EV67 instruction.
       There are no additional instructions available on the EV7 processor,
       but the compiler does have different instruction scheduling and
       prefetch rules for tuning code for the EV7.

       Applications compiled with this option may incur emulation
       overhead on EV4, EV5, EV56, and PCA56 processors.

  Beginning with OpenVMS Alpha V7.1 and continuing with subsequent
  versions, the operating system includes an instruction emulator.
  This capability allows any Alpha chip  to  execute  and  produce
  correct  results  from  Alpha instructions - even if the some of
  the instructions are not implemented on the chip.   Applications
  using  emulated  instructions  will run correctly, but may incur
  significant emulation overhead at run time.  Emulation  for  the
  BWX  (byte  and word) instructions was included in OpenVMS Alpha
  V7.1.    Emulation   for   the   floating-point   square   root,
  integer/floating-point   register   transfer,   and   bit  count
  instructions will be included in  a  version  of  OpenVMS  Alpha
  after V7.2.